A team of researchers has built and operated a probabilistic computer with 1 million probabilistic bits, or p-bits, the largest such machine ever demonstrated. The system, described in a study published July 18, 2026, uses off-the-shelf field-programmable gate arrays (FPGAs) rather than exotic cryogenic hardware, marking a distinct architectural path from the superconducting and trapped-ion systems dominating quantum computing headlines.
The machine does not perform quantum computation. It operates at room temperature, uses classical CMOS circuits, and is designed to accelerate specific optimization and sampling problems—the same class of workloads quantum computers target, but without requiring error correction or vacuum chambers. The question is whether scale alone can make probabilistic computing commercially relevant before fault-tolerant quantum machines arrive.
What They're Actually Building
Probabilistic bits, or p-bits, are a computational primitive introduced by Supriyo Datta and Kerem Camsari at Purdue University. Unlike a classical bit that is deterministically 0 or 1, a p-bit fluctuates between states with a controllable probability distribution. A network of interconnected p-bits can perform a form of Markov Chain Monte Carlo sampling that maps naturally onto combinatorial optimization problems—think traveling salesman, graph partitioning, or Boltzmann machine training.
The 1-million-p-bit system is built from a cluster of Xilinx FPGAs, each emulating thousands of p-bits in digital logic. The architecture uses a sparse, reconfigurable interconnection fabric that approximates the all-to-all connectivity ideal for Ising-model computations. The team reports the system can update all 1 million p-bits in approximately 1 microsecond, yielding an effective p-bit-flip rate of roughly 10¹² per second across the full array.
This is not a universal computer. It is a domain-specific accelerator for probabilistic inference and optimization. The roadmap targets 10 million p-bits within two years, with a long-term goal of 100 million p-bits using ASIC implementations that would reduce per-bit power consumption below 1 milliwatt. For calibration: D-Wave's latest Advantage2 annealing quantum processor operates with roughly 7,000 qubits. IBM's quantum roadmap targets 100,000 qubits by 2033. The p-bit architecture is already at 1 million nodes, albeit with a fundamentally different—and more limited—computational model.
Winners and Losers
The most immediate competitive pressure lands on D-Wave Systems, which has built its business on quantum annealing for optimization. A room-temperature, FPGA-based probabilistic computer that scales to 1 million nodes challenges D-Wave's value proposition directly, particularly for customers who prioritize time-to-solution over theoretical quantum advantage. D-Wave's systems require cryogenic cooling, shielded environments, and specialized facilities. The p-bit machine runs in a standard server rack.
NTT Research and Hitachi, both of which have invested in Ising-machine architectures including coherent Ising machines and CMOS annealers, face a similar dynamic. Their systems have demonstrated strong performance on specific benchmarks but have not reached this node count. The 1-million-p-bit milestone resets the scale conversation.
For the gate-model quantum computing leaders—IBM, Google Quantum AI, IonQ, Quantinuum—the threat is indirect but real. If probabilistic computers can deliver practical optimization results at scale before fault-tolerant quantum computers arrive, the near-term commercial market for quantum optimization services could shrink. That said, p-bit systems cannot run Shor's algorithm, simulate quantum chemistry, or perform other applications requiring genuine quantum superposition and entanglement. The addressable market overlap is partial, not total.
FPGA vendors, particularly AMD-Xilinx and Intel-Altera, benefit from this architecture. The 1-million-p-bit machine is essentially a demonstration that reconfigurable logic can compete with purpose-built quantum hardware on specific workloads. Cloud providers offering FPGA instances—AWS F1, Azure NP-series—could integrate p-bit IP blocks as accelerator options, creating a distribution channel that bypasses dedicated quantum hardware entirely.
The Bigger Picture
This announcement lands in a 2026 landscape where quantum computing investment has cooled from its 2024-2025 peak. Several high-profile quantum startups have pivoted to classical-quantum hybrid solutions or shut down entirely. Venture funding for pure-play quantum hardware companies declined roughly 30% year-over-year in the first half of 2026, according to PitchBook data. In this environment, a room-temperature, FPGA-based architecture that scales to 1 million nodes and targets revenue-generating optimization workloads looks pragmatically attractive.
Government investment continues: the U.S. CHIPS Act has allocated $500 million specifically for quantum and emerging computing architectures through 2027, and the EU Quantum Flagship's next phase includes €200 million for alternative computing paradigms. Probabilistic computing fits within these mandates, though it competes for the same pool of non-dilutive funding that quantum hardware startups rely on.
For calibration, consider Fujitsu's Digital Annealer, which reached a 100,000-bit scale in 2023 and has been deployed commercially for logistics and drug discovery workloads. The 1-million-p-bit system represents a 10x node-count increase over that benchmark. Separately, NTT's coherent Ising machine demonstrated 100,000 spins in 2024. The p-bit architecture now holds the scale record among all Ising-inspired computing platforms, quantum or classical.
The Signal
The signal here is that probabilistic computing is separating from quantum computing as a distinct, commercially viable track for optimization workloads. The 1-million-p-bit milestone is genuinely significant for the Ising-machine community, but it does not represent progress toward universal quantum computation. Calling this a "quantum alternative" is marketing, not physics. What this reveals is a growing bifurcation: fault-tolerant quantum computing remains a decade-scale project, while domain-specific probabilistic accelerators are scaling rapidly on established semiconductor fabrication and packaging infrastructure.
The specific technical milestone that would validate this approach is a demonstrable wall-clock speedup over classical solvers on a commercially relevant optimization benchmark—not just asymptotic scaling arguments or simulated performance projections. The team has not yet published such a benchmark against Gurobi or CPLEX on a standard problem set. Until that comparison exists, the 1-million-p-bit number is a capacity claim, not a performance claim.
"In short: probabilistic computing with 1 million p-bits demonstrates that Ising-machine architectures can scale on commodity hardware, but the absence of benchmarked performance against classical solvers leaves the commercial value unproven."